ModelProjects

所属分类VHDL/FPGA/Verilog
开发工具:Others
文件大小:67KB
澳门威尼斯人官网次数:252
上传日期:2007-05-26 22:50:42
上 传 者刘伟
说明:  实现了图像处理的Verilog级,包含有七个主要 文件
(image processing to achieve the level of Verilog, contains seven key documents)

文件列表:[ 举报垃圾]
ModelProjects
............. \bak
.............\...\colorChange.v. bak
.............\...\exMain.v. bak
.............\...\funcCtrl.v. bak
.............\...\imageProc.v. bak
.............\...\ImageProcess.cr. mti
.............\...\positionChange.v. bak
.............\...\ramIn.v. bak
.............\...\ramOut.v. bak
.............\
.............\colorChange.v. bak
.............\
.............\exMain.v. bak
.............\
.............\imageProc.cr. mti
.............\imageProc. mpf
.............\
.............\imageProc.v. bak
.............\
.............\MyTest.v. bak
.............\
.............\MyTest_ColorChanger.v. bak
.............\
.............\positionChange.v. bak
.............\
.............\ramIn.v. bak
.............\
.............\ramOut.v. bak
.............\
.............\TestBench_ColorChanger.v. bak
.............\
.............\vsim. wlf
.............\
............. \work
.............\.... \@my@test
.............\....\........\verilog. asm
.............\....\........\_primary. dat
.............\....\........\_primary. vhd
.............\.... \@my@test_@color@changer
.............\....\.......................\verilog. asm
.............\....\.......................\_primary. dat
.............\....\.......................\_primary. vhd
.............\.... \color@changer
.............\....\.............\verilog. asm
.............\....\.............\_primary. dat
.............\....\.............\
.............\.... \color@changer@test
.............\....\..................\verilog. asm
.............\....\..................\_primary. dat
.............\....\..................\
.............\.... \ex@main@proc
.............\....\............\verilog. asm
.............\....\............\_primary. dat
.............\....\............\
.............\.... \func@controller
.............\....\...............\verilog. asm
.............\....\...............\_primary. dat
.............\....\...............\
.............\.... \image@processor
.............\....\...............\verilog. asm
.............\....\...............\_primary. dat
.............\....\...............\_primary. vhd
.............\.... \position@changer
.............\....\................\verilog. asm
.............\....\................\_primary. dat
.............\....\................\
.............\.... \ram@in
.............\....\......\verilog. asm
.............\....\......\_primary. dat
.............\....\......\
.............\.... \ram@out
.............\....\.......\verilog. asm
.............\....\.......\_primary. dat
.............\....\.......\
.............\....\

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